The present disclosure relates to a method and a corresponding device for synchronizing the data transmission between two circuits. One embodiment is designed according to different circuit engineering principles, for example CMOS and bipolar circuit engineering.
The interconnection of CMOS (Complementary Metal Oxide Semiconductor) modules and bipolar modules poses major problems, for example in high frequency circuits, since in CMOS circuits, inter alia, the operating time tolerances, due to variations in temperature and supply voltage, are significantly greater than in bipolar circuits. Without the use of a balancing interface, therefore, the synchronization of data and clock between the different circuits would be lost. The abovementioned problem is conventionally solved by so-called elastic-store interfaces, a corresponding example of which is shown in FIG. 1.
FIG. 1 illustrates a CMOS module 1 that writes n-bit-data DATA1 with its CMOS-clock CLK1 in a buffer memory 10, and a bipolar module 2 later reads out or collects the buffered data in the buffer memory 10 with its bipolar clock CLK2 in the form of n-Bit-data DATA2, in order to be able to process this further. At no point in time should a write and a read access be taking place at the same memory cell of the buffer memory 10, since otherwise during a read process the bit stored in the immediately preceding write cycle could be overwritten by the new write cycle. Therefore in the example shown in FIG. 1 offset read and write address counters 11 or 13 are used, so that the undesired overwriting of the memory cells of the buffer memory 10 described above can be reliably avoided. The write addresses generated by the write address counter 11 are stored via a decoder 12 at the individual memory cells of the buffer memory 10, while the read address counter 13 for reading out of the buffered data drives a multiplexer 14. The memory depth of the buffer memory 10, that is, the number of memory cells present, is essentially dependent upon the CMOS tolerances, and the buffer memory 10 can, for example, have a memory depth of 6 (as in the example Illustrated in FIG. 1), 8 or 12.
When such an elastic store interface with circuit components 10-14 is used, the associated space requirement is relative high. In particular, the buffer memory 10, which works according to the FIFO (First In-First Out) principle, is relatively space-intensive and also increases by the power dissipation. All n information channels, usually 8 or 16 bit, must be stored in a correspondingly large memory field of the buffer memory 10 (with a bus width of 16 bits and a memory depth of 6, for example, a total of 96 flip-flops will be needed for this).